Electronic Design

EDA Update: C-To-VHDL High-Level Synthesis Tool

A C-TO-VHDL high-level synthesis tool is now downloadable from the Center for Embedded Computing Systems of the University of California, Irvine. Called SPARK, it takes the behavior of an application ...
EDN

IEEE approves ALF, synthesis standards

SANTA CRUZ, Calif. — Paving the way for greater library and EDA tool interoperability, the IEEE has approved Accellera's Advanced Library Format (ALF) and Verilog and VHDL synthesis subsets as new ...
EDN

EDA entrepreneur spins $750 VHDL simulator

Santa Cruz, Calif. — A part-time passion for affordable HDL simulation led Cypress Semiconductor engineer Haneef Mohammed to launch Symphony EDA, which last week rolled out what it calls a ...
Semiconductor Engineering

IEEE 1076-VHSIC HW Description Language

VHDL was an offshoot of the VHSIC (Very High-Speed IC) program, funded by the U.S. Department of Defense (DoD), and was first proposed in 1981. Language development was done by Intermetrics Inc, who ...